CBSE UGC NET Computer Science Paper III Solved December 2015 - Part 1

1.       The three outputs x1x2x3 from the 8x3 priority encoder are used to provide a vector address of the form 101x1x2x300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority?
(A) BC                (B) A4
(C) BD               (D) AC
2.       What will be the output at PORT1 if the following program is executed?
MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT
(A) 37H              (B) 82H
(C) B9H             (D) 00H
Explanation:
In 8085 programming, the result of an operation is stored in the accumulator.
So output is 82H.
3.       Which of the following 8085 microprocessor hardware interrupt has the lowest priority?
(A) RST 6.5                   (B) RST 7.5
(C) TRAP                      (D) INTR
4.       A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?
(A) 0.64              (B) 0.96
(C) 2.00             (D) 0.32
Explanation:
in 1ms :  refresh = 32 times
Memory cycle = 1ms/250ns   = 106ns/250ns = 4000 times
Therefore, % of refresh time  = (32 x 100ns)/(4000 x 250ns)
= 3200ns/1000000 x 100% = 0.32%
5.       A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
(A) 0.06%          (B) 0.12%
(C) 1.2%            (D) 2.5%
Explanation:
The DMA combines one word from four consecutive characters (bytes) so we get
4800 chars/s = 4800 bytes/s = 1200 words/s (one word = 32 bits = 4 bytes)

If we assume that one CPU instruction is one word wide then
1 million instructions/s = 1 million words/s = 106 word/s

So we have 1200 words received during one second and (106-1200) words processed by the CPU (while DMA is transferring a word, the CPU cannot fetch the instruction so we have to subtract the number of words transferred by DMA).
While DMA transfer CPU executes only 106 - 1200 = 998800 instructions
[998800 / 106] * 100 = 99.88 %
Slowdown = 100 - 99.88 = 0.12%

The CPU will be slowed down by 0.12%.

6.       A CPU handles interrupt by executing interrupt service subroutine.................
(A) by checking interrupt register after execution of each instruction
(B) by checking interrupt register at the end of the fetch cycle
(C) whenever an interrupt is registered
(D) by checking interrupt register at regular time interval
7.       Given the following set of prolog clauses:
father(X, Y):
parent(X, Y),
male(X),
parent(Sally, Bob),
parent(Jim, Bob),
parent(Alice, Jane),
parent(Thomas, Jane),
male(Bob),
male(Jim),
female(Salley),
female(Alice).
How many atoms are matched to the variable ‘X’ before the query
father(X, Jane) reports a Result?
(A) 1       (B) 2
(C) 3       (D) 4
8.       Forward chaining systems are ............. where as backward chaining systems are ................
(A) Data driven, Data driven              (B) Goal driven, Data driven
(C) Data driven, Goal driven              (D) Goal driven, Goal driven
9.       Match the following w.r.t. programming languages:
List - I                                     List – II
(a) JAVA                        (i) Dynamically object oriented
(b) Python                     (ii) Statically Non-object oriented
(c) Prolog                      (iii) Statically object oriented
(d) ADA                         (iv) Dynamically non-object oriented
Codes:
(a)  (b)  (c)  (d)
(A) (iii)  (i)   (ii)  (iv)
(B) (i)   (iii)  (ii)  (iv)
(C) (i)   (iii)  (iv) (ii)
(D) (ii)  (iv)  (i)   (iii)
10.    The combination of an IP address and a port number is known as ...................
(A) network number                (B) socket address